1. Field of the Invention
The present invention relates to a method of designing a semiconductor integrated circuit device of a hierarchical placement and hierarchical routing, and a hierarchical placement and global routing system, in a standard cell or gate array method.
2. Description of the Related Art
In a method of designing a semiconductor integrated circuit device of a hierarchical placement and global routing system and a hierarchical placement and global routing system in a conventional standard cell or gate array method, a logical connection description having a hierarchical structure is expanded in advance into a flat level. Thereafter, the hierarchy structure is divided into areas corresponding to sizes of blocks defined on a chip. The other method is that a module having hierarchy of height is artificially created and arranged as a block to separate from other blocks.
However, when a logical connection description is made, a designer is skilled in contents of logical connections. As a result, the designer often makes a logical connection description in a bottom-up manner based on the content of a logical connection. Alternatively he often takes a connection previously used into a part of the logical connection description. In a conventional automatic dividing method, originally meaningful hierarchies must be destroyed into the flat level, and the module having the hierarchy must be divided again to rebuild hierarchical structure of higher level regardless of the original meanings.
Once a layout is completed, a logical connection must often be partially corrected due to a logical connection description error or timings. In this case, an initial description does not correspond to blocks on the layout and is inconsistent. Therefore, although the designer is skilled in the contents of logical connections, he cannot correct only one block and must lay out the entire chip again.